As is known, for performing complex processing functions, associative memories with cells capable of memorizing a number of analog or digital multibit values are currently being studied, and for which use is advantageously made of nonvolatile floating-gate cells, particularly flash-EEPROMs, in which the value to be memorized is related to the threshold voltage of the cell. To read the cells, memorize the analog data and perform the processing operations, the cells must therefore be supplied through a specific input circuit with a number of appropriately memorized analog voltages.
According to one known solution (U.S. Pat. No. 4,232,302), the input circuit comprises a sample-and-hold circuit having one input, N outputs and N+1 temporary storage paths and a control circuit that provides for cyclically coupling the input to the temporary storage paths to load all the analog input values sequentially on to the temporary storage paths and supply them cyclically to the output. In view of the time taken to load the analog voltages and supply them to the output, the above circuit is unsuitable for applications involving the storage and/or reading of a large number of multi level analog or digital signals.